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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">Interrupt Masks<div class="ingroups"><a class="el" href="group__group__i2s.html">I2S          (Inter-IC Sound)</a> &raquo; <a class="el" href="group__group__i2s__macros.html">Macros</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga3bcfda6db2e4dd7bf3138542b4eea44f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga3bcfda6db2e4dd7bf3138542b4eea44f">CY_I2S_INTR_TX_TRIGGER</a>&#160;&#160;&#160;(I2S_INTR_TX_TRIGGER_Msk)</td></tr>
<tr class="memdesc:ga3bcfda6db2e4dd7bf3138542b4eea44f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 0: Less entries in the TX FIFO than specified by Trigger Level.  <a href="#ga3bcfda6db2e4dd7bf3138542b4eea44f">More...</a><br /></td></tr>
<tr class="separator:ga3bcfda6db2e4dd7bf3138542b4eea44f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26ffe69252c2c4252bf0f2f8406e7f0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga26ffe69252c2c4252bf0f2f8406e7f0b">CY_I2S_INTR_TX_NOT_FULL</a>&#160;&#160;&#160;(I2S_INTR_TX_NOT_FULL_Msk)</td></tr>
<tr class="memdesc:ga26ffe69252c2c4252bf0f2f8406e7f0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 1: TX FIFO is not full.  <a href="#ga26ffe69252c2c4252bf0f2f8406e7f0b">More...</a><br /></td></tr>
<tr class="separator:ga26ffe69252c2c4252bf0f2f8406e7f0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc2be4eeee3e8b5a0d54bd6e881f5218"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#gadc2be4eeee3e8b5a0d54bd6e881f5218">CY_I2S_INTR_TX_EMPTY</a>&#160;&#160;&#160;(I2S_INTR_TX_EMPTY_Msk)</td></tr>
<tr class="memdesc:gadc2be4eeee3e8b5a0d54bd6e881f5218"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 4: TX FIFO is empty, i.e.  <a href="#gadc2be4eeee3e8b5a0d54bd6e881f5218">More...</a><br /></td></tr>
<tr class="separator:gadc2be4eeee3e8b5a0d54bd6e881f5218"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga334a1ab0b685497edc4bf132400814a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga334a1ab0b685497edc4bf132400814a8">CY_I2S_INTR_TX_OVERFLOW</a>&#160;&#160;&#160;(I2S_INTR_TX_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga334a1ab0b685497edc4bf132400814a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 5: Attempt to write to a full TX FIFO.  <a href="#ga334a1ab0b685497edc4bf132400814a8">More...</a><br /></td></tr>
<tr class="separator:ga334a1ab0b685497edc4bf132400814a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38b517292ead00d3848962fa7fca7eb5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga38b517292ead00d3848962fa7fca7eb5">CY_I2S_INTR_TX_UNDERFLOW</a>&#160;&#160;&#160;(I2S_INTR_TX_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga38b517292ead00d3848962fa7fca7eb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 6: Attempt to read from an empty TX FIFO.  <a href="#ga38b517292ead00d3848962fa7fca7eb5">More...</a><br /></td></tr>
<tr class="separator:ga38b517292ead00d3848962fa7fca7eb5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f368e82f9c84ba941019890f6483519"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga8f368e82f9c84ba941019890f6483519">CY_I2S_INTR_TX_WD</a>&#160;&#160;&#160;(I2S_INTR_TX_WD_Msk)</td></tr>
<tr class="memdesc:ga8f368e82f9c84ba941019890f6483519"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 8: Tx watchdog event occurs.  <a href="#ga8f368e82f9c84ba941019890f6483519">More...</a><br /></td></tr>
<tr class="separator:ga8f368e82f9c84ba941019890f6483519"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4fa10b6befda1cb14e09a9114e2e5200"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga4fa10b6befda1cb14e09a9114e2e5200">CY_I2S_INTR_RX_TRIGGER</a>&#160;&#160;&#160;(I2S_INTR_RX_TRIGGER_Msk)</td></tr>
<tr class="memdesc:ga4fa10b6befda1cb14e09a9114e2e5200"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 16: More entries in the RX FIFO than specified by Trigger Level.  <a href="#ga4fa10b6befda1cb14e09a9114e2e5200">More...</a><br /></td></tr>
<tr class="separator:ga4fa10b6befda1cb14e09a9114e2e5200"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab58d434d0f9ef5bc1dce8c211cede677"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#gab58d434d0f9ef5bc1dce8c211cede677">CY_I2S_INTR_RX_NOT_EMPTY</a>&#160;&#160;&#160;(I2S_INTR_RX_NOT_EMPTY_Msk)</td></tr>
<tr class="memdesc:gab58d434d0f9ef5bc1dce8c211cede677"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 18: RX FIFO is not empty.  <a href="#gab58d434d0f9ef5bc1dce8c211cede677">More...</a><br /></td></tr>
<tr class="separator:gab58d434d0f9ef5bc1dce8c211cede677"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3ab58981323c1646276eb0e53fc0e3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#gaa3ab58981323c1646276eb0e53fc0e3f">CY_I2S_INTR_RX_FULL</a>&#160;&#160;&#160;(I2S_INTR_RX_FULL_Msk)</td></tr>
<tr class="memdesc:gaa3ab58981323c1646276eb0e53fc0e3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 19: RX FIFO is full.  <a href="#gaa3ab58981323c1646276eb0e53fc0e3f">More...</a><br /></td></tr>
<tr class="separator:gaa3ab58981323c1646276eb0e53fc0e3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga688ee43b09fb7c608997eb8f510b4fe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga688ee43b09fb7c608997eb8f510b4fe8">CY_I2S_INTR_RX_OVERFLOW</a>&#160;&#160;&#160;(I2S_INTR_RX_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga688ee43b09fb7c608997eb8f510b4fe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 21: Attempt to write to a full RX FIFO.  <a href="#ga688ee43b09fb7c608997eb8f510b4fe8">More...</a><br /></td></tr>
<tr class="separator:ga688ee43b09fb7c608997eb8f510b4fe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14e9d7cfaf29a9ab998e6bfc15971d45"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga14e9d7cfaf29a9ab998e6bfc15971d45">CY_I2S_INTR_RX_UNDERFLOW</a>&#160;&#160;&#160;(I2S_INTR_RX_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga14e9d7cfaf29a9ab998e6bfc15971d45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 22: Attempt to read from an empty RX FIFO.  <a href="#ga14e9d7cfaf29a9ab998e6bfc15971d45">More...</a><br /></td></tr>
<tr class="separator:ga14e9d7cfaf29a9ab998e6bfc15971d45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a1c19138ee16c467ccbe3fc36fc75ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__i2s__macros__interrupt__masks.html#ga0a1c19138ee16c467ccbe3fc36fc75ec">CY_I2S_INTR_RX_WD</a>&#160;&#160;&#160;(I2S_INTR_RX_WD_Msk)</td></tr>
<tr class="memdesc:ga0a1c19138ee16c467ccbe3fc36fc75ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 24: Rx watchdog event occurs.  <a href="#ga0a1c19138ee16c467ccbe3fc36fc75ec">More...</a><br /></td></tr>
<tr class="separator:ga0a1c19138ee16c467ccbe3fc36fc75ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga3bcfda6db2e4dd7bf3138542b4eea44f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3bcfda6db2e4dd7bf3138542b4eea44f">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_TRIGGER</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_TRIGGER&#160;&#160;&#160;(I2S_INTR_TX_TRIGGER_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 0: Less entries in the TX FIFO than specified by Trigger Level. </p>

</div>
</div>
<a id="ga26ffe69252c2c4252bf0f2f8406e7f0b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga26ffe69252c2c4252bf0f2f8406e7f0b">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_NOT_FULL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_NOT_FULL&#160;&#160;&#160;(I2S_INTR_TX_NOT_FULL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 1: TX FIFO is not full. </p>

</div>
</div>
<a id="gadc2be4eeee3e8b5a0d54bd6e881f5218"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadc2be4eeee3e8b5a0d54bd6e881f5218">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_EMPTY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_EMPTY&#160;&#160;&#160;(I2S_INTR_TX_EMPTY_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 4: TX FIFO is empty, i.e. </p>
<p>it has 0 entries. </p>

</div>
</div>
<a id="ga334a1ab0b685497edc4bf132400814a8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga334a1ab0b685497edc4bf132400814a8">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_OVERFLOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_OVERFLOW&#160;&#160;&#160;(I2S_INTR_TX_OVERFLOW_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 5: Attempt to write to a full TX FIFO. </p>

</div>
</div>
<a id="ga38b517292ead00d3848962fa7fca7eb5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga38b517292ead00d3848962fa7fca7eb5">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_UNDERFLOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_UNDERFLOW&#160;&#160;&#160;(I2S_INTR_TX_UNDERFLOW_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 6: Attempt to read from an empty TX FIFO. </p>
<p>This happens when the IP is ready to transfer data and TX_EMPTY is '1'. </p>

</div>
</div>
<a id="ga8f368e82f9c84ba941019890f6483519"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8f368e82f9c84ba941019890f6483519">&#9670;&nbsp;</a></span>CY_I2S_INTR_TX_WD</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_TX_WD&#160;&#160;&#160;(I2S_INTR_TX_WD_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 8: Tx watchdog event occurs. </p>

</div>
</div>
<a id="ga4fa10b6befda1cb14e09a9114e2e5200"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4fa10b6befda1cb14e09a9114e2e5200">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_TRIGGER</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_TRIGGER&#160;&#160;&#160;(I2S_INTR_RX_TRIGGER_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 16: More entries in the RX FIFO than specified by Trigger Level. </p>

</div>
</div>
<a id="gab58d434d0f9ef5bc1dce8c211cede677"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab58d434d0f9ef5bc1dce8c211cede677">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_NOT_EMPTY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_NOT_EMPTY&#160;&#160;&#160;(I2S_INTR_RX_NOT_EMPTY_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 18: RX FIFO is not empty. </p>

</div>
</div>
<a id="gaa3ab58981323c1646276eb0e53fc0e3f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa3ab58981323c1646276eb0e53fc0e3f">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_FULL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_FULL&#160;&#160;&#160;(I2S_INTR_RX_FULL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 19: RX FIFO is full. </p>

</div>
</div>
<a id="ga688ee43b09fb7c608997eb8f510b4fe8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga688ee43b09fb7c608997eb8f510b4fe8">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_OVERFLOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_OVERFLOW&#160;&#160;&#160;(I2S_INTR_RX_OVERFLOW_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 21: Attempt to write to a full RX FIFO. </p>

</div>
</div>
<a id="ga14e9d7cfaf29a9ab998e6bfc15971d45"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga14e9d7cfaf29a9ab998e6bfc15971d45">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_UNDERFLOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_UNDERFLOW&#160;&#160;&#160;(I2S_INTR_RX_UNDERFLOW_Msk)</td>
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      </table>
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<p>Bit 22: Attempt to read from an empty RX FIFO. </p>

</div>
</div>
<a id="ga0a1c19138ee16c467ccbe3fc36fc75ec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0a1c19138ee16c467ccbe3fc36fc75ec">&#9670;&nbsp;</a></span>CY_I2S_INTR_RX_WD</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_I2S_INTR_RX_WD&#160;&#160;&#160;(I2S_INTR_RX_WD_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 24: Rx watchdog event occurs. </p>

</div>
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